The present invention relates to three-dimensional (3D) chip assemblies, and more specifically, to TSV implants in 3D chip assemblies.
Advancements in the area of semiconductor fabrication have enabled the manufacturing of integrated circuits with a high density of electronic components. However, the increasing numbers and lengths of interconnect wirings may cause an increase in circuit resistance-capacitance delay and power consumption, which may impact circuit performance. Three-dimensional (3D) stacking of integrated circuits address these challenges.
Fabricating 3D integrated circuits includes vertically stacking at least two silicon wafers. Vertically stacking the wafers may reduce interconnect wiring length and increase semiconductor device density. Deep through-silicon/substrate vias (TSVs) may be formed to provide interconnections and electrical connectivity between the electronic components of the 3D integrated circuits. Such TSVs may have high aspect ratios, in which the via height is large with respect to the via width, to save valuable area in an integrated circuit design. Therefore, semiconductor device density may be increased, and total length of interconnect wiring may be decreased by incorporating TSVs in 3D integrated circuits.
In order to form an electrical connection between the components of two silicon wafers stacked one on top of the other, a TSV may extend through the entire thickness of a single wafer. More specifically, a TSV may extend through multiple interconnect levels and through a semiconductor substrate in which semiconductor devices may be formed. The interconnect levels may generally be located above the substrate and include multiple connections to and between the devices formed in the substrate. To form the TSV, a deep trench is etched into the wafer through the interconnect levels and the substrate.